This invention relates to data processing apparatus provided with data transmitting and receiving units.
Data processing apparatus which exchanges data between it and another data processing apparatus and between it and a controller including peripheral apparatus is generally provided with means for converting parallel data into series data so as to transmit and receive data over a single data line, thus decreasing the number of data lines. In most cases, such series data transmitting and receiving units are fabricated as an integrated circuit in the form of an input/output section of a central processing unit (CPU) which processes the parallel data and the input/output circuit is formed on the same substrate as the CPU.
Field of application of such data processing apparatus is very wide and the apparatus is frequently used for such machines and apparatus wherein exchange of source battery can not be made readily. Accordingly, it became necessary to construct all of the data processing apparatus with complementary type field effect transistor circuits capable of operating with a low power consumption and to stop the operation of the apparatus during an interval other than that necessary to process the data thus decreasing the power consumption as far as possible.
However, since the prior art data processing apparatus equipped with series data transmitting and receiving unit operates in synchronism with a fundamental clock pulse such as a system clock pulse while the series data transmitting and receiving unit is operating to transmit and receive the data, transistors in the CPU that constitute the data processing unit are operated by the fundamental clock pulse independently of the program control, thus consuming large power. Since the CPU is constituted by such many circuit elements as a logic arithmetic operation circuit, counters and various registers, when these elements operate independently of the program control, excessive power would be consumed.
Furthermore, in the prior art series data transmission and reception the judgement as to whether the transmission of the data has completed or not is made when the CPU supplies to the data transmitting and receiving unit a transfer completion confirmation signal. For example, such judgement is made by constructing the circuit such that the fundamental clock pulse is constantly supplied to the CPU, and that the content of a shift register, for example, of the transmitting and receiving section adapted to exchange data between it and the CPU, is applied to a counter and that as the counter overflows a flag is operated to apply to the CPU an interruption instruction representing completion of transfer. As a consequence, the capacity of the program is increased for executing the interruption instruction thereby complicating the circuit construction.